1. Field
The present invention relates to the field of semiconductor manufacturing, specifically a through via contact formation process, which features a multi-step etch to create a via contact with an integral bump.
2. Description of Related Art
Currently, progress has been made in increasing chip processing power by stacking wafers containing different circuit functions, such as memory, logic, analog and digital.
One challenge to mass producing high-density, vertically integrated modules has been forming die interconnects within a vertical chip stack. Flip-chip does not allow for interconnecting more than two chips, and wire bonding is limited to the number of chips that can be stacked, requiring manufacturers to link chips over edges.
Conventional processes have been used to form uniform bumps on thin silicon substrates to connect multiple chips for an array of applications. However, these processes require multiple masks, plating, and CMP steps. Therefore, a new method is needed to ensure uniformity between through via contacts for use in thin substrates with fewer manufacturing steps.